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fractional-n frequency synthesizer ADF4153 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features rf bandwidth 500 mhz to 4 ghz 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage programmable dual-modulus prescaler 4/5, 8/9 programmable charge pump currents 3-wire serial interface analog and digital lock detect power-down mode pin compatible with the adf4110/adf4111/adf4112/adf4113 and adf4106 programmable modulus on fractional-n synthesizer trade-off noise versus spurious performance applications catv equipment base stations for mobile radio (gsm, pcs, dcs, cdma, wcdma) wireless handsets (gsm, pcs, dcs, cdma, wcdma) wireless lans communications test equipment general description the ADF4153 is a fractional-n frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. it consists of a low noise digital phase frequency detector (pfd), a precision charge pump, and a programmable reference divider. there is a - based fractional interpolator to allow programmable fractional-n division. the int, frac, and mod registers define an over all n divider (n = (int + (frac/mod))). in addition, the 4-bit reference counter (r counter) allows selectable refin frequencies at the pfd input. a complete phase-locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (vco). control of all on-chip registers is via a simple 3-wire interface. the device operate with a power supply ranging from 2.7 v to 3.3 v and can be powered down when not in use. functional block diagram lock detect n-counter cp rfcp3 rfcp2 rfcp1 reference data le 24-bit data register clock ref in av dd agnd v dd v dd dgnd r div n div dgnd cpgnd dv dd v p sdv dd r set rf in a rf in b output mux muxout ? + high z phase frequency detector ADF4153 third order fractional interpolator modulus reg fraction reg integer reg current setting 2 doubler 4-bit r counter charge pump 03685-a-001 figure 1.
ADF4153 rev. a | page 2 of 24 table of contents specifications..................................................................................... 3 timing characteristics..................................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and pin function descriptions...................... 7 typical performance characteristics ............................................. 8 circuit description......................................................................... 10 reference input section............................................................. 10 rf input stage............................................................................. 10 rf int divider........................................................................... 10 int, frac, mod, and r relationship.................................... 10 rf r counter ........................................................................ 10 phase frequency detector (pfd) and charge pump............ 11 muxout and lock detect................................................... 11 input shift registers ................................................................... 11 program modes .......................................................................... 11 n divider register, r0 ............................................................... 17 r divider register, r1................................................................ 17 control register, r2 ................................................................... 17 noise and spur register, r3 ...................................................... 18 reserved bits............................................................................... 18 rf synthesizer: a worked example ........................................ 18 modulus....................................................................................... 19 reference doubler and reference divider ............................. 19 12-bit programmable modulus................................................ 19 spurious optimization and fastlock ....................................... 19 phase resync and spur consistency ....................................... 19 spurious signalspredicting where they will appear....... 20 filter designadisimpll....................................................... 20 interfacing ................................................................................... 20 pcb design guidelines for chip scale package .................... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 1/04data sheet changed from a rev. 0 to a rev. a renumbered figures and tables.............................. universal changes to specifications ............................................................... 3 changes to pin function description .......................................... 7 changes to rf power-down section .......................................... 17 changes to pcb design guidelines for chip scale package section .............................................................................. 21 updated outline dimensions ...................................................... 22 updated ordering guide.............................................................. 22 7/03revision 0: initial version
ADF4153 rev. a | page 3 of 24 specifications 1 av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 ?. table 1. parameter b version unit test conditions/comments rf characteristics (3 v) see figure 17 for input circuit. rf input frequency (rf in ) 2 0.5/4.0 ghz min/max ?8 dbm/0 dbm min/max. for lower frequencies, ensure slew rate (sr) > 396 v/s. 1.0/4.0 ghz min/max ?10 dbm/0 dbm min/max. reference characteristics s ee figure 16 for input circuit. ref in input frequency 2 10/250 mhz min/max for f < 10 mhz, use a dc-coupled cmos compatible square wave, slew rate > 21 v/s. ref in input sensitivity 0.7/av dd v p-p min/max ac-coupled. 0 to av dd v max cmos compatible. ref in input capacitance 10 pf max ref in input current 100 a max phase detector phase detector frequency 3 32 mhz max charge pump i cp sink/source programmable. see table 5. high value 5 ma typ with r set = 5.1 k?. low value 312.5 a typ absolute accuracy 2.5 % typ with r set = 5.1 k?. r set range 1.5/10 k? min/max i cp three-state leakage current 1 na typ sink and source current. matching 2 % typ 0.5 v < v cp < v p C 0.5. i cp vs. v cp 2 % typ 0.5 v < v cp < v p C 0.5. i cp vs. temperature 2 % typ v cp = v p /2. logic inputs v inh , input high voltage 1.4 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage 1.4 v min open-drain 1 k? pull-up to 1.8 v. v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 2.7/3.3 v min/v max dv dd , sdv dd av dd v p av dd /5.5 v min/v max i dd 4 24 ma max 20 ma typical. low power sleep mode 1 a typ noise characteristics phase noise figure of merit 5 ?217 dbc/hz typ ADF4153 phase noise floor 6 ?147 dbc/hz typ @ 10 mhz pfd frequency. ?143 dbc/hz typ @ 26 mhz pfd frequency. phase noise performance 7 @ vco output. 1750 mhz output 8 ?106 dbc/hz typ @ 1 khz offs et, 26 mhz pfd frequency. see footnotes on next page.
ADF4153 rev. a | page 4 of 24 1 operating temperature is b version: ?40c to +80c. 2 use a square wave for frequencies below f min . 3 guaranteed by design. sample tested to ensure compliance. 4 ac coupling ensures av dd /2 bias. see figure 16 for typical circuit. 5 this figure can be used to calculate phase noise for any application. use the formula C217 + 10log(f pfd ) + 20logn to calculate in-band phase noise performance as seen at the vco output. the value given is the lowest noise mode. 6 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0logn (where n is the n divider value). the value given is the lowest noise mode. 7 the phase noise is measured with the eval-ADF4153eb1 evaluation board and the hp8562e spectrum analyzer. 8 f refin = 26 mhz; f pfd = 10 mhz; offset frequency = 1 khz; rf out = 1750 mhz; n = 175; loop b/w = 20 khz; lowest noise mode.
ADF4153 rev. a | page 5 of 24 timing characteristics 1 av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 ?. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width 1 guaranteed by design but not production tested. cloc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04414-0-002 figure 2. timing diagram
ADF4153 rev. a | page 6 of 24 absolute maximum ratings 1, 2, 3, 4 t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +4 v v dd to v dd ?0.3 v to +0.3 v v p to gnd ?0.3 v to +5.8 v v p to v dd ?0.3 v to +5.8 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in , rf in to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b versio n) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c tssop ja thermal impedance 150.4c/w lfcsp ja thermal impedance (paddle soldered) 122c/w lfcsp ja thermal impedance (pa ddle not soldered) 216c/w lead temperature, soldering vapor phase (60 sec) 215c infrared 220c 1 stresses above those listed under absolute maximum ratings may ca use permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. ex posure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high performan ce rf integrated circuit with an esd rating of < 2 kv, and it is esd sensitive. proper precauti ons should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v. 4 v dd = av dd = dv dd = sdv dd . esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADF4153 rev. a | page 7 of 24 pin configuration and pi n function descriptions ADF4153 top view (not to scale) agnd 4 rf in b 5 rfi in a 6 av dd 7 ref in 8 le data clk sdv dd dgnd 13 12 11 10 r set 1 cp 2 cpgnd 3 v p dv dd muxout 16 15 14 9 03685-a-002 figure 3. tssop pin configuration 03685-a-003 15 14 13 12 cpgnd 1 agnd 2 agnd 3 cp 11 muxout le data clk sdv dd av dd 6 av dd 7 ref in 8 dgnd 9 dgnd 10 rf in b4 rf in a5 r set v p dv d d dv d d 19 18 17 16 20 19 17 16 pin 1 indicator ADF4153 top view figure 4. lfcsp pin configuration table 4. pin function descriptions tssop lfcsp mnemonic description 1 19 r set connecting a resistor between this pin and ground sets the maximum charge pump output current. the relation ship between i cp and r set is set cp r 5 25 i . max = with r set = 5.1 k?, i cpmax = 5 ma. 2 20 cp charge pump output. when enabled, this provides i cp to the external loop filter, which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf pres caler. this point should be deco upled to the ground plane with a small bypass capacitor, typically 100 pf (see figure 17). 6 5 rf in a input to the rf prescaler. th is small-signal input is normally ac-coupled from the vco. 7 6, 7 av dd positive power supply for the rf section. decoupling capacitors to the digital ground plane should be placed as close as po ssible to this pin. av dd has a value of 3 v 10%. av dd must have the same voltage as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k? (see figure 16). this input can be driven from a ttl or cmos crystal oscillator, or it can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 sdv dd -? power. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. sdv dd has a value of 3 v 10%. sdv dd must have the same voltage as dv dd . 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the regist ers. the data is latched into the shift register on the clk rising edge . this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le is high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 15 muxout this multiplexer output allows either the rf lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd positive power supply for the digital section. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd has a value of 3 v 10%. dv dd must have the same voltage as av dd . 16 18 v p charge pump power supply. this shou ld be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v.
ADF4153 rev. a | page 8 of 24 typical performance characteristics figure 5 to figure 10: rf out = 1.722 ghz, pfd freq = 26 mhz, int = 66, channel spacing = 200 khz, modulus = 130, fraction = 1/130, and i cp = 5 ma. loop bandwidth = 20 khz, reference = fox 10 mhz tcxo, vco = vari-l vco190-1750t, eval board = eval-ADF4153eb1, measurements taken on hp8562e spectrum analyzer. output power (db) 0 ?30 ?50 ?80 ?90 ?100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest noise mode n = 66 1/130 rbw = 10hz reference level = ?4dbm ?102dbc/hz ?2khz ?1khz 1khz 2khz 1.722ghz 03685-a-004 figure 5. phase noise (lowest noise mode) output power (db) 0 ?30 ?50 ?80 ?90 ?100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz low noise and spur mode n = 66 1/130 rbw = 10hz reference level = ?4.2dbm ?95dbc/hz ?2khz ?1khz 1khz 2khz 1.722ghz 03685-a-005 figure 6. phase noise (low noise mode and spur mode) output power (db) 0 ?30 ?50 ?80 ?90 ?100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest spur mode n = 66 1/130 rbw = 10hz reference level = ?4.2dbm ?90dbc/hz ?2khz ?1khz 1khz 2khz 1.722ghz 03685-a-006 figure 7. phase noise (lowest spur mode) output power (db) 0 ?30 ?50 ?80 ?90 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest noise mode n = 66 1/130 rbw = 10hz reference level = ?4.2dbm ?71dbc@200khz ?400khz ?200khz 200khz 400khz 1.722ghz ?100 03685-a-007 figure 8. spurs (lowest noise mode) output power (db) 0 ?30 ?50 ?80 ?90 ?100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz low noise and spur mode n = 66 1/130 rbw = 10hz reference level = ?4.2dbm ?74dbc@200khz ?400khz ?200khz 200khz 400khz 1.722ghz 03685-a-008 figure 9. spurs (low noise and spur mode) output power (db) 0 ?30 ?50 ?80 ?90 ?100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest spur noise n = 66 1/130 rbw = 10hz reference level = ?4.2dbm ?400khz ?200khz 200khz 400khz 1.722ghz 03685-a-009 figure 10. spurs (lowest spur mode)
ADF4153 rev. a | page 9 of 24 phase noise (dbc/hz) phase detector frequency (khz) ?130 ?140 ?150 ?160 ?170 100 1000 10000 100000 03685-a-010 figure 11. pfd noise floor vs. pfd frequency (lowest noise mode) frequency (ghz) amplitude (dbm) 5 0 ?5 ?10 ?20 ?15 ?25 ?30 ?35 0 0.5 1.0 1.5 4.0 3.5 3.0 2.5 2.0 4.5 p = 4/5 p = 8/9 03685-a-011 figure 12. rf input sensitivity v cp (v) 6 0 ?6 i cp (ma) 4 2 ?2 ?4 ?5 ?3 ?1 1 3 5 012345 03685-a-012 figure 13. charge pump output characteristics r set value (k ? ) ?80 ?85 ?110 035 30 25 20 15 10 5 phase noise (dbc/hz) ?90 ?95 ?105 ?100 03685-a-013 figure 14. phase noise vs. r set temperature(c) ?90 ?94 ?104 ?60 100 ?40 phase noise (dbc/hz) ?20 0 20 40 60 ?96 ?98 ?92 ?102 ?100 80 03685-a-014 figure 15. phase noise vs. temperature
ADF4153 rev. a | page 10 of 24 circuit description reference input section the reference input stage is shown in figure 16. sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. 04414-0-010 buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control figure 16. reference input stage rf input stage the rf input stage is shown in figure 17. it is followed by a 2-stage limiting amplifier to generate the current mode logic (cml) clock levels needed for the prescaler. bias generator 1.6v agnd av dd 2k ? 2k ? rf in b rf in a 03685-a-015 figure 17. rf input stage rf int divider the rf int cmos counter allows a division ratio in the pll feedback counter. division ratios from 31 to 511 are allowed. int, frac, mod, and r relationship the int, frac, and mod values, in conjunction with the r counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (pfd). see the rf synthesizer: a worked example section for more information. the rf vco frequency ( rf out ) equation is ( ) ( ) mod frac int f rf pfd out + = (1) where rf out is the output frequency of external voltage controlled oscillator (vco). ( ) r d ref f in pfd + = 1 (2) where: ref in is the reference input frequency. d is the ref in doubler bit. r is the preset divide ratio of binary 4-bit programmable reference counter (1 to 15). int is the preset divide ratio of binary 9-bit counter (31 to 511). mod is the preset modulus ratio of binary 12-bit programmable frac counter (2 to 4095). frac is the preset fractional ratio of binary 12-bit programmable frac counter (0 to mod). rf r counter the 4-bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 15 are allowed. third order fractional interpolator frac value mod reg int reg rf n divider n = int + frac/mod from rf input stage to pfd n-counter 03685-a-016 figure 18. a and b counters
ADF4153 rev. a | page 11 of 24 phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 19 is a simplified schematic. the pfd includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function, and gives a consistent reference spur level. u3 clr2 q2 d2 u2 down up hi hi cp ?in + in charge pump delay clr1 q1 d1 u1 03685-a-017 figure 19. pfd simplified schematic muxout and lock detect the output multiplexer on the ADF4153 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 (see table 8). figure 20 shows the muxout section in block diagram form. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k? nominal. when lock has been detected, it is high with narrow low-going pulses. digital lock detect r counter output logic low dgnd control mux muxout dv dd three-state output n counter output analog lock detect logic high 03685-a-018 figure 20. muxout schematic input shift registers the ADF4153 digital section includes a 4-bit rf r counter, a 9- bit rf n counter, a 12-bit frac counter, and a 12-bit modulus counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2 and c1) in the shift register. these are the 2 lsbs, db1 and db0, as shown in figure 2. the truth table for these bits is shown in table 5. table 6 shows a summary of how the latches are programmed. program modes table 5 through table 10 show how to set up the program modes in the ADF4153. the ADF4153 programmable modulus is double buffered. this means that two events have to occur before the part uses a new modulus value. first, the new modulus value is latched into the device by writing to the r divider register. second, a new write must be performed on the n divider register. therefore, any time that the modulus value has been updated, the n divider register must be written to after this, to ensure that the modulus value is loaded correctly. table 5. c2 and c1 truth table control bits c2 c1 register 0 0 n divider register 0 1 r divider register 1 0 control register 1 1 noise and spur register
ADF4153 rev. a | page 12 of 24 table 6. register summary noise and spur reg db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 t2 t3 t4 t5 t6 t7 t8 noise and spur mode db2 t9 noise and spur mode reserved n divider reg db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 n1 n3 n4 n5 n6 control bits control bits control bits control bits 12-bit fractional value (frac) db23 db22 db21 n7 n8 n9 9-bit integer value (int) n2 fastlock fl1 r divider reg db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 r1 r3 r4 12-bit interpolator modulus value (mod) 4-bit r counter r2 muxout p2 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load control reserved reserved prescaler control reg reference doubler db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 s1 s2 s3 s4 cp current setting pd polarity resync ldp power- down cp three-state counter reset db15 cp3 cp/2 03685-a-019
ADF4153 rev. a | page 13 of 24 table 7. n divider register map f12 f11 f10 f3 f2 f1 fractional value (frac) 0 .......... 0 0 .......... 0 0 .......... 0 0 .......... 0 . .......... . . .......... . . .......... . 1 .......... 1 4092 1 .......... 1 4093 1 .......... 1 4094 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 2 3 . . . 0 1 0 1 .......... 1 4095 n9 n8 n7 n6 n5 n4 n3 n2 n1 integer value (int) 000 1131 001 0032 001 0133 001 0034 ... ... ... ... ... ... 1 1 1 1 1 509 1 1 1 1 0 510 1 0 0 0 0 . . . 1 1 111 1 0 0 0 . . . 1 1 1 1 0 0 0 . . ... 1 1 11 1 0 0 1 . . . 0 1 1 1 511 fl1 fastlock 0 normal operation 1 fast lock enabled db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 n1 n3 n4 n5 n6 control bits 12-bit fractional value (frac) db23 db22 db21 n7 n8 n9 9-bit integer value (int) n2 fast lock fl1 03685-a-020
ADF4153 rev. a | page 14 of 24 table 8. r divider register map m12 interpolator modulus value (mod) m11 m10 m3 m2 m1 0 0 .......... 0 1 0 2 0 0 .......... 0 1 1 3 0 0 .......... 1 0 0 4 . . .......... . . . . . . .......... . . . . . . .......... . . . . 1 1 .......... 1 0 0 4092 1 1 .......... 1 0 1 4093 1 1 .......... 1 1 0 4094 1 0 0 0 . . . 1 1 1 1 1 .......... 1 1 1 4095 rf r counter divide ratio r4 r3 r2 r1 0 0 0 0 . . . 112 113 114 1 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 1 2 3 4 . . . 0 1 0 115 p1 prescaler 0 4/5 1 8/9 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 r1 r3 r4 control bits 12-bit interpolator modulus value (mod) 4-bit r counter r2 muxout p2 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load control reserved prescaler p3 load control 0 normal operation 1 load resync m3 m2 m1 muxout 0 three-state output digital lock detect analog lock detect 0 0 n divider output logic high logic low 0 1 r divider output 1 1 fastlock switch 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 03685-a-021
ADF4153 rev. a | page 15 of 24 table 9. control register map u3 power-down 0 normal operation 1 power-down u4 ldp 0 1 3 5 i cp (ma) cp3 cp2 cp1 cp0 2.7k ? 5.1k ? 10k ? 0 1.09 0.63 0.29 0 2.18 1.25 0.59 0 3.26 1.88 0.88 0 4.35 2.50 1.15 0 5.44 3.13 1.47 0 6.53 3.75 1.76 0 7.62 4.38 2.06 0 8.70 5.00 2.35 1 0.54 0.31 0.15 1 1.10 0.63 0.30 1 1.64 0.94 0.44 1 2.18 1.25 0.588 1 2.73 1.57 0.74 1 3.27 1.88 0.88 1 3.81 2.19 1.03 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4.35 2.50 1.18 u5 pd polarity 0 negative 1 positive u2 cp three-state 0 disabled 1 three-state u1 counter reset 0 disabled enabled 1 reference doubler u6 0 disabled 1 enabled reference double db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 s1 s2 s3 s4 control bits cp current setting pd polarity resync ldp power- down cp three-state counter reset db15 cp3 cp/2 s4 s3 s2 s1 resync 011 002 013 ... ... ... 1113 1014 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1115 03685-a-022
ADF4153 rev. a | page 16 of 24 table 10. noise and spur register lowest spur mode 00000 low noise and spur mode 11100 lowest noise mode 11111 db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 t2 t3 t4 t5 t6 t7 t8 control bits noise and spur mode db2 t9 noise and spur mode reserved reserved reserved db10, db5, db4, db3 noise and spur setting db9, db8, db7, db6, db2 reserved 0 these bits must be set to 0 for normal operation. 03685-a-023
ADF4153 rev. a | page 17 of 24 n divider register, r0 with r0[1, 0] set to [0, 0], the on-chip n divider register is programmed. table 7 shows the input data format for programming this register. 9-bit int value these nine bits control what is loaded as the int value. this is used to determine the overall feedback division factor. it is used in equation 1. 12-bit frac value these 12 bits control what is loaded as the frac value into the fractional interpolator. this is part of what determines the overall feedback division factor. it is used in equation 1. the frac value must be less than or equal to the value loaded into the mod register. fastlock when set to logic high, this enables the fastlock. this sets the charge pump current to its maximum value. when set to logic low, the charge pump current is equal to the value programmed in the function register. r divider register, r1 with r1[1, 0] set to [0, 1], the on-chip r divider register is programmed. table 8 shows the input data format for programming this register. load control when set to logic high, the value being programmed in the modulus is not loaded into the modulus. instead, it sets the resync delay of the -. this is done to ensure phase resync when changing frequencies. see the phase resync and spur consistency section for more information and a worked example. muxout the on-chip multiplexer is controlled by r1[22 ... 20] on the ADF4153. table 8 shows the truth table. digital lock detect the digital lock detect output goes high if there are 40 successive pfd cycles with an input error of less than 15 ns. it stays high until a new channel is programmed or until the error at the pfd input exceeds 30 ns for one or more cycles. if the loop bandwidth is narrow compared to the pfd frequency, the error at the pfd inputs may drop below 15 ns for 40 cycles around a cycle slip. therefore, the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. in this case, the digital lock detect is reliable only as a loss-of-lock detector. prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the int, frac, and mod counters, determines the overall division ratio from the rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 2 ghz. therefore, when operating the ADF4153 above 2 ghz, this must be set to 8/9. the prescaler limits the int value. with p = 4/5, n min = 31. with p = 8/9, n min = 91. the prescaler can also influence the phase noise performance. if int < 91, a prescaler of 4/5 should be used. for applications where int > 91, p = 8/9 should be used for optimum noise performance (see table 8). 4-bit rf r counter the 4-bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 15 are allowed. 12-bit interpolator modulus this programmable register sets the fractional modulus. this is the ratio of the pfd frequency to the channel step resolution on the rf output. refer to the rf synthesizer: a worked example section for more information. the ADF4153 programmable modulus is double buffered. this means that two events have to occur before the part uses a new modulus value. first, the new modulus value is latched into the device by writing to the r divider register. second, a new write must be performed on the n divider register. therefore, any time that the modulus value has been updated, the n divider register must be written to after this, to ensure that the modulus value is loaded correctly. control register, r2 with r2[1, 0] set to [0, 1], the on-chip control register is programmed. table 9 shows the input data format for programming this register. rf counter reset db3 is the rf counter reset bit for the ADF4153. when this is 1, the rf synthesizer counters are held in reset. for normal operation, this bit should be 0. rf charge pump three-state this bit puts the charge pump into three-state mode when programmed to 1. it should be set to 0 for normal operation. rf power-down db4 on the ADF4153 provides the programmable power-down mode. setting this bit to 1 performs a power-down. setting this bit to 0 returns the synthesizer to normal operation. while in software power-down mode, the part retains all information in its registers. only when supplies are removed are the register contents lost.
ADF4153 rev. a | page 18 of 24 when a power-down is activated, the following events occur: 1. all active dc current paths are removed. 2. the synthesizer counters are forced to their load state conditions. 3. the charge pump is forced into three-state mode. 4. the digital lock detect circuitry is reset. 5. the rf in input is debiased. 6. the input register remains active and capable of loading and latching data. lock detect precision (ldp) when this bit is programmed to 0, three consecutive reference cycles of 15 ns must occur before digital lock detect is set. when this bit is programmed to 1, five consecutive reference cycles of 15 ns must occur before digital lock detect is set. phase detector polarity db6 in the ADF4153 sets the phase detector polarity. when the vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. charge pump current setting db7, db8, and db9 set the charge pump current setting. this should be set to the charge pump current that the loop filter is designed with (see table 9). ref in doubler setting this bit to 0 feeds the ref in signal directly to the 4-bit rf r counter, disabling the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 4-bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest noise mode and in the lowest noise and spur mode. the phase noise is insensitive to ref in duty cycle when the doubler is disabled. noise and spur register, r3 with r3[1, 0] set to 1, 1, the on-chip noise and spur register is programmed. table 10 shows the input data format for programming this register. noise and spur mode noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. when the lowest spur setting is chosen, dither is enabled. this randomizes the fractional quantization noise so that it looks more like white noise rather than spurious noise. this means that the part is optimized for improved spurious performance. this operation would normally be used when the pll closed-loop bandwidth is wide, for fast-locking applications. (wide-loop bandwidth is seen as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res )). a wide-loop filter does not attenuate the spurs to a level that a narrow-loop bandwidth would. when the low noise and spur setting is enabled, dither is disabled. this optimizes the synthesizer to operate with improved noise performance. however, the spurious performance is degraded in this mode compared to the lowest spurs setting. to further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. as well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. this setting is extremely useful where a narrow-loop filter bandwidth is available. the synthesizer ensures extremely low noise and the filter attenuates the spurs. the typical performance characteristics give the user an idea of the trade-off in a typical wcdma setup for the different noise and spur settings. reserved bits these bits should be set to 0 for normal operation. rf synthesizer: a worked example this equation governs how the synthesizer should be programmed. ( ) [ ] [] pfd out f mod frac int rf + = (3) where: rf out is the rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. ( ) [ ] r d ref f in pfd + = 1 (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor.
ADF4153 rev. a | page 19 of 24 example: in a gsm 1800 system, where 1.8 ghz rf frequency output (rf out ) is required, a 13 mhz reference frequency input (ref in ) is available and a 200 khz channel resolution (f res ) is required on the rf output. 65 200 13 = = = khz mhz mod f ref mod res in from equation 4: ( ) [ ] mhz mhz f pfd 13 1 0 1 13 = + = (5) ( ) 30 ; 138 65 13 8 . 1 = = + = frac int frac int mhz g (6) modulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the channel resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in would set the modulus to 65. this means that the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. reference doubler an d reference divider the reference doubler on-chip allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually results in an improvement in noise performance of 3 db. it is important to note that the pfd cannot be operated above 32 mhz due to a limitation in the speed of the - circuit of the n divider. 12-bit programmable modulus unlike most other fractional-n plls, the ADF4153 allows the user to program the modulus over a 12-bit range. this means that the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 4-bit r counter. for example, here is an application that requires 1.75 ghz rf and 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible setup is feeding the 13 mhz directly to the pfd and programming the modulus to divide by 65. this would result in the required 200 khz resolution. another possible setup is using the reference doubler to create 26 mhz from the 13 mhz input signal. this 26 mhz is then fed into the pfd. the modulus is now programmed to divide by 130. this also results in 200 khz resolution and offers superior phase noise performance over the previous setup. the programmable modulus is also very useful for multi- standard applications. if a dual-mode phone requires pdc and gsm 1800 standards, the programmable modulus is a huge benefit. pdc requires 25 khz channel step resolution, whereas gsm 1800 requires 200 khz channel step resolution. a 13 mhz reference signal could be fed directly to the pfd. the modulus would be programmed to 520 when in pdc mode (13 mhz/ 520 = 25 khz). the modulus would be reprogrammed to 65 for gsm 1800 operation (13 mhz/65 = 200 khz). it is important that the pfd frequency remains constant (13 mhz). this allows the user to design one loop filter that can be used in both setups without running into stability issues. it is the ratio of the rf frequency to the pfd frequency that affects the loop design. keeping this relationship constant, instead of changing the modulus factor, results in a stable filter. spurious optimization and fastlock as mentioned earlier, the part can be optimized for spurious performance. however, in fast locking applications, the loop bandwidth needs to be wide, and therefore the filter does not provide much attenuation of the spurs. the programmable charge pump can be used to get around this issue. the filter is designed for a narrow-loop bandwidth so that steady-state spurious specifications are met. this is designed using the lowest charge pump current setting. to implement fastlock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump. this has the effect of widening the loop bandwidth, which improves lock time. when the pll has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting. this narrows the loop bandwidth to its original cutoff frequency to allow better attenuation of the spurs than the wide-loop bandwidth. phase resync and spur consistency setting the resync bits [s4 ,s3, s2, and s1] enables the phase resync feature. with a fractional denominator of mod, a fractional-n pll can settle with any one of (2 )/mod valid phase offsets with respect to the reference input. this is different from integer-n where the rf output always settles to the same static phase offset with respect to the input reference, which is zero ideally. this is not an issue in applications that require only a consistent frequency lock. when resync is enabled, it also ensures that spur levels remain consistent when the pll returns to a certain frequency. this is due to the fact that the resync function resets the - modulator. resync is enabled by setting the s4 to s1 bits in r2 to a nonzero value. when the s4 to s1 bits are 0, 0, 0, and 0, resync is disabled. for applications where a consistent phase relationship between the output and reference is required (i.e., digital beam forming), the ADF4153 can be used with the phase resync feature enabled. this ensures that if the user programs the pll to jump from frequency (and phase) a to frequency (and phase) b and back again to frequency a, the pll returns to the original phase (phase a).
ADF4153 rev. a | page 20 of 24 when enabled, it activates every time the user programs register r0 to set a new output frequency. however, if a cycle slip occurs in the settling transient after the phase resync operation, the phase resync is lost. this can be avoided by delaying the resync activation until the locking transient is close to its final frequency. this is done by rewriting to r1 after r1 has been set up as normal. setting load control [db23] allows this. when set, instead of determining the fractional denominator, the mod bits [m12 to m1] are used to set a time interval from when the new channel is programmed to the time the resync is activated. this is called the delay. its value should be programmed to set a time interval that is at least as long as the rf pll lock time. for example, if ref in = 26 mhz and mod = 130 to give 200 khz output steps (f res ), and the rf loop has a settling time of 150 s, then delay should be programmed to 3,900, as 26 mhz 150 s = 3,900. if the application requires the delay to be greater than 4095, the resync bits should be increased. for example, if the lock time above is 1.5 ms, the delay should be programmed to 26 mhz 1.5 ms = 39,000. in this case, program m12 to m1 to 3,900 and program s4 to s1 to 10. the delay is 3,900 10 = 39,000. spurious signalspredicting where they will appear just as in integer-n plls, spurs appear at pfd frequency offsets from the carrier. in a fractional-n pll, spurs also appear at frequencies equal to the rf out channel step resolution (f res ). the third-order fractional interpolator engine of the ADF4153 may also introduce subfractional spurs. if the fractional denominator (mod) is divisible by 2, spurs appear at 1/2 f res. if the fractional denominator (mod) is divisible by 3, spurs appear at 1/3 f res. harmonics of all spurs mentioned will also appear. with the lowest spur mode enabled, the fractional and subfractional spurs is attenuated dramatically. the worst-case spurs appear when the fraction is programmed to (1/mod). for example, in a gsm 900 mhz system with a 26 mhz pfd frequency and an rf out channel step resolution (f res ) of 200 khz, the mod = 130. pfd spurs appear at 26 mhz offset, and fractional spurs appear at 200 khz offset. since mod is divisible by 2, subfractional spurs are also present at 100 khz offset. filter designadisimpll a filter design and analysis program is available to help the user to implement pll design. visit www.analog.com/pll for a free download of the adisimpll software. the software designs, simulates, and analyzes the entire pll frequency domain and time domain response. various passive and active filter architectures are allowed. rev. #2 of adisimpll allows analysis of the ADF4153. interfacing the ADF4153 has a simple spi? compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) is high, the 22 bits that have been clocked into the input register on each rising edge of sclk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz or one update every 1.1 s. this is more than adequate for systems that have typical lock times in the hundreds of microseconds. aduc812 interface figure 21 shows the interface between the ADF4153 and the aduc812 microconverter?. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the ADF4153 needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the microconverter to the device. after the third byte is written, the le input should be brought high to complete the transfer. when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 180 khz. aduc812 ADF4153 sclock sclk sdata le muxout (lock detect) mosi i/o ports 03685-a-024 figure 21. aduc812 to ADF4153 interface
ADF4153 rev. a | page 21 of 24 adsp-2181 interface figure 22 shows the interface between the ADF4153 and the adsp-21xx digital signal processor. as discussed previously, the ADF4153 needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. adsp-21xx ADF4153 sclock sclk sdata le muxout (lock detect) dt tfs i/o flags 03685-a-025 figure 22. adsp-21xx to ADF4153 interface pcb design guidelines for chip scale package the lands on the chip scale package (cp-20) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
ADF4153 rev. a | page 22 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab figure 23. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 1 20 5 6 11 16 15 bottom view 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.0 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 figure 24. 20-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body (cp-20) dimensions shown in millimeters ordering guide model description temperature range package option ADF4153bru thin shrink small outline package (tssop) ?40c to +85c ru-16 ADF4153bru-reel thin shrink small outline package (tssop) ?40c to +85c ru-16 ADF4153bru-reel7 thin shrink small outlin e package (tssop) ?40c to +85c ru-16 ADF4153bcp lead frame chip scale pa ckage (lfcsp) ?40c to +85c cp-20 ADF4153bcp-reel lead frame chip scale package (lfcsp) ?40c to +85c cp-20 ADF4153bcp-reel7 lead frame chip scale package (lfcsp) ?40c to +85c cp-20 eval-ADF4153eb1 evaluation board
ADF4153 rev. a | page 23 of 24 notes
ADF4153 rev. a | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03685C0C1/04(a)

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